LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY adder4 IS
PORT(
  a,b:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
  cin:IN STD_LOGIC;
  s:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
  cout:OUT STD_LOGIC);
END adder4; 
ARCHITECTURE adder4p OF adder4 IS
COMPONENT adder1                           
  PORT(
  a,b:IN STD_LOGIC;
  cin:IN STD_LOGIC;
  s:OUT STD_LOGIC;
  cout:OUT STD_LOGIC);
END COMPONENT; 
SIGNAL temp:STD_LOGIC_VECTOR(3 DOWNTO 0);
  BEGIN
    add0: adder1 port map(a=>a(0),b=>b(0),cin=>cin,cout=>temp(0),s=>s(0));
    add1: adder1 port map(a=>a(1),b=>b(1),cin=>cin,cout=>temp(1),s=>s(1));
    add2: adder1 port map(a=>a(2),b=>b(2),cin=>cin,cout=>temp(2),s=>s(2));
    add3: adder1 port map(a=>a(3),b=>b(3),cin=>cin,cout=>temp(3),s=>s(3));
END adder4p;





